DeterministicESPAsyncWebServer v6.27.1
Zero-allocation, bounded-execution async HTTP server for ESP32
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iface_bridge_hw.h File Reference

ESP32 glue for the interface bridge (DETWS_ENABLE_IFACE_BRIDGE): the PROTO_BRIDGE listener that wires an accepted connection to a UART / SPI / I2C endpoint, plus the bus I/O. More...

#include "ServerConfig.h"

Go to the source code of this file.

Detailed Description

ESP32 glue for the interface bridge (DETWS_ENABLE_IFACE_BRIDGE): the PROTO_BRIDGE listener that wires an accepted connection to a UART / SPI / I2C endpoint, plus the bus I/O.

The pure core (iface_bridge.h) owns the rule table and the transaction frame codec; this file owns the side that touches hardware: a ConnProto::PROTO_BRIDGE connection handler and the Serial / SPI / Wire transfers. Layered exactly like services/relay - the app opens the listener, then publishes a target:

int32_t li = server.listen(2323, ConnProto::PROTO_BRIDGE); // front port 2323
BridgeTarget uart = {BridgeBus::uart, BridgeMode::stream, 1, 0, 115200, 0, 0};
det_bridge_publish((uint8_t)li, 2323, BridgeProto::tcp, &uart); // -> UART1 raw passthrough
int32_t ls = server.listen(2324, ConnProto::PROTO_BRIDGE);
BridgeTarget spi = {BridgeBus::spi, BridgeMode::transaction, 0, 5, 1000000, 0, 0}; // 5 = CS gpio
det_bridge_publish((uint8_t)ls, 2324, BridgeProto::tcp, &spi); // -> SPI write-then-read frames
@ PROTO_BRIDGE
address:port -> hardware bus (DETWS_ENABLE_IFACE_BRIDGE): UART/SPI/I2C device server.

Security: a published port is a direct pipe to the bus. Only expose it on a trusted interface / behind an upstream ACL; there is no authentication at this layer.

Author
Douglas Quigg (dstroy0)
Date
2026

Definition in file iface_bridge_hw.h.