DeterministicESPAsyncWebServer v6.27.1
Zero-allocation, bounded-execution async HTTP server for ESP32
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iface_bridge_hw.h
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1// Copyright (C) 2026 Douglas Quigg (dstroy0) <dquigg123@gmail.com>
2// SPDX-License-Identifier: AGPL-3.0-or-later
3
4/**
5 * @file iface_bridge_hw.h
6 * @brief ESP32 glue for the interface bridge (DETWS_ENABLE_IFACE_BRIDGE): the PROTO_BRIDGE listener that
7 * wires an accepted connection to a UART / SPI / I2C endpoint, plus the bus I/O.
8 *
9 * The pure core (iface_bridge.h) owns the rule table and the transaction frame codec; this file owns the
10 * side that touches hardware: a ConnProto::PROTO_BRIDGE connection handler and the Serial / SPI / Wire
11 * transfers. Layered exactly like services/relay - the app opens the listener, then publishes a target:
12 *
13 * @code
14 * int32_t li = server.listen(2323, ConnProto::PROTO_BRIDGE); // front port 2323
15 * BridgeTarget uart = {BridgeBus::uart, BridgeMode::stream, 1, 0, 115200, 0, 0};
16 * det_bridge_publish((uint8_t)li, 2323, BridgeProto::tcp, &uart); // -> UART1 raw passthrough
17 *
18 * int32_t ls = server.listen(2324, ConnProto::PROTO_BRIDGE);
19 * BridgeTarget spi = {BridgeBus::spi, BridgeMode::transaction, 0, 5, 1000000, 0, 0}; // 5 = CS gpio
20 * det_bridge_publish((uint8_t)ls, 2324, BridgeProto::tcp, &spi); // -> SPI write-then-read frames
21 * @endcode
22 *
23 * Security: a published port is a direct pipe to the bus. Only expose it on a trusted interface / behind
24 * an upstream ACL; there is no authentication at this layer.
25 *
26 * @author Douglas Quigg (dstroy0)
27 * @date 2026
28 */
29
30#ifndef DETERMINISTICESPASYNCWEBSERVER_IFACE_BRIDGE_HW_H
31#define DETERMINISTICESPASYNCWEBSERVER_IFACE_BRIDGE_HW_H
32
33#include "ServerConfig.h"
34
35#if DETWS_ENABLE_IFACE_BRIDGE
36
38#include <stdint.h>
39
40/**
41 * @brief Bind a PROTO_BRIDGE listener to a hardware target and install the handler (first call).
42 *
43 * Registers the rule in the pure table (bridge_map), records the listener_id -> rule binding used to
44 * dispatch accepted connections, and brings up the bus (Serial.begin / SPI CS pin / Wire).
45 *
46 * @param listener_id the id returned by `server.listen(port, ConnProto::PROTO_BRIDGE)`.
47 * @param port the same listen port (the dispatch key into the rule table).
48 * @param proto TCP or UDP (matches how the listener was opened).
49 * @param target the UART / SPI / I2C endpoint (copied into the rule).
50 * @return true; false if @p target is null, the rule table is full, or the port+proto is already bound.
51 */
52bool det_bridge_publish(uint8_t listener_id, uint16_t port, BridgeProto proto, const BridgeTarget *target);
53
54/** @brief Clear all listener bindings and rules (start from empty). */
55void det_bridge_listener_reset(void);
56
57#endif // DETWS_ENABLE_IFACE_BRIDGE
58
59#endif // DETERMINISTICESPASYNCWEBSERVER_IFACE_BRIDGE_HW_H
User-facing configuration for DeterministicESPAsyncWebServer.
User-defined address:port -> hardware-bus translation (DETWS_ENABLE_IFACE_BRIDGE).