iface_bridge.h File Reference

User-defined address:port -> hardware-bus translation (PROTOCORE_ENABLE_IFACE_BRIDGE). More...

#include "protocore_config.h"

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Detailed Description

User-defined address:port -> hardware-bus translation (PROTOCORE_ENABLE_IFACE_BRIDGE).

A configurable "device server": the application registers rules mapping a listen address:port (plus TCP/UDP) to a hardware endpoint - a UART, an SPI chip-select, or an I2C address - so a network client talking to x.x.x.x:nnnn is transparently bridged to that bus. Two payload models:

• STREAM (UART): raw bidirectional passthrough. Socket bytes are written to the UART and UART bytes flow back to the socket, with no framing (a classic serial-device server / ser2net).
• TRANSACTION (SPI / I2C, also usable for UART): the socket carries framed write-then-read transactions, which is what master-initiated buses need. Each request frame is uint16 write_len (big-endian) || uint16 read_len (big-endian) || write_bytes[write_len] and the reply is the read_len bytes clocked/read back. The bus address (I2C 7-bit addr) or chip-select (SPI CS gpio) + clock/mode come from the rule's target, so the frame stays generic.

This header is the pure, host-tested core: the fixed-capacity rule table (zero heap) and the transaction frame codec. The actual bus I/O (uart.h / spi.h / i2c.h) and the PROTO_BRIDGE listener are the bus step (iface_bridge_hw.*), kept separate exactly like the peripheral services.

Author

Douglas Quigg (dstroy0)

Date

2026

Definition in file iface_bridge.h.