ProtoCore v0.0.1
Deterministic, zero-heap network stack for embedded targets
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board_profile.h
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1// Copyright (C) 2026 Douglas Quigg (dstroy0) <dquigg123@gmail.com>
2// SPDX-License-Identifier: AGPL-3.0-or-later
3
4/**
5 * @file board_profile.h
6 * @brief Per-variant default sizing: pick sane PC_* defaults for the target board.
7 *
8 * The library's sizing defaults used to be a single flat set tuned to fit the smallest
9 * classic-ESP32 DRAM ceiling, so a board with far more RAM/flash silently inherited the
10 * same cramped numbers. This selector instead layers per-variant default files:
11 *
12 * - chip variant (classic / s3 / c6 / p4) - HW-specific switches + chip-appropriate
13 * defaults (internal SRAM, core count, crypto HW accel).
14 * - PSRAM size (8 / 16 / 32 MB) - RAM-backed buffer sizes; a given chip
15 * ships with or without PSRAM, so it is its own axis.
16 * - flash size (8 / 16 / 32 MB) - flash-backed sizing; likewise independent.
17 *
18 * Every default is set behind an `#ifndef`, so precedence is "first definition wins":
19 * your -D / build_opt.h override > PSRAM profile > flash profile > chip profile
20 * (chip files pull in classic_defaults.h last as the universal floor). Nothing here forces
21 * a value you set yourself.
22 *
23 * Chip is auto-detected from the SoC target macro. PSRAM/flash size can't be read reliably
24 * from the Arduino core, so set them for your board (they default to "none / smallest"):
25 * @code
26 * build_flags = -DPC_PSRAM_MB=8 -DPC_FLASH_MB=16
27 * @endcode
28 * ESP-IDF builds auto-fill both from the sdkconfig below.
29 */
30
31#ifndef PROTOCORE_BOARD_PROFILE_H
32#define PROTOCORE_BOARD_PROFILE_H
33
34// The chip / flash / PSRAM selection below keys off the ESP-IDF sdkconfig macros (CONFIG_IDF_TARGET_*,
35// CONFIG_ESPTOOLPY_FLASHSIZE_*, CONFIG_SPIRAM_SIZE). sdkconfig.h is NOT force-included in every translation
36// unit, and protocore_config.h pulls this header in before any esp/Arduino header - so a TU that includes
37// protocore_config.h first (e.g. tls.cpp) would see none of those macros and EVERY board would silently fall
38// through to the classic floor (wrong sizing + HW-accel flags, and inconsistent with TUs that happen to pull
39// an Arduino header in first). Pull sdkconfig.h in here when it is on the include path (all ESP-IDF /
40// Arduino-ESP32 builds have it) so the detection is include-order-independent. It is absent on host/native
41// builds, where the classic profile is the correct choice anyway.
42#if defined(__has_include)
43#if __has_include("sdkconfig.h")
44#include "sdkconfig.h"
45#endif
46#endif
47
48// The one vendor/die selector: derives PC_VENDOR_ESP / _STM / _RP / _TI / _HOST from the toolchain target
49// macros so the per-vendor partitioning keys off PC_VENDOR_* instead of re-testing CONFIG_IDF_TARGET_* here.
50#include "pc_platform.h"
51
52// --- flash size (MB): honor an explicit -DPC_FLASH_MB, else read the ESP-IDF sdkconfig ---
53#if !defined(PC_FLASH_MB)
54#if defined(CONFIG_ESPTOOLPY_FLASHSIZE_32MB)
55#define PC_FLASH_MB 32
56#elif defined(CONFIG_ESPTOOLPY_FLASHSIZE_16MB)
57#define PC_FLASH_MB 16
58#elif defined(CONFIG_ESPTOOLPY_FLASHSIZE_8MB)
59#define PC_FLASH_MB 8
60#elif defined(CONFIG_ESPTOOLPY_FLASHSIZE_4MB)
61#define PC_FLASH_MB 4
62#elif defined(CONFIG_ESPTOOLPY_FLASHSIZE_2MB)
63#define PC_FLASH_MB 2
64#endif
65#endif
66
67// --- PSRAM size (MB): honor an explicit -DPC_PSRAM_MB, else read the ESP-IDF sdkconfig ---
68#if !defined(PC_PSRAM_MB) && defined(CONFIG_SPIRAM_SIZE)
69#if CONFIG_SPIRAM_SIZE >= (32 * 1024 * 1024)
70#define PC_PSRAM_MB 32
71#elif CONFIG_SPIRAM_SIZE >= (16 * 1024 * 1024)
72#define PC_PSRAM_MB 16
73#elif CONFIG_SPIRAM_SIZE >= (8 * 1024 * 1024)
74#define PC_PSRAM_MB 8
75#elif CONFIG_SPIRAM_SIZE >= (4 * 1024 * 1024)
76#define PC_PSRAM_MB 4
77#elif CONFIG_SPIRAM_SIZE >= (2 * 1024 * 1024)
78#define PC_PSRAM_MB 2
79#endif
80#endif
81
82// --- PSRAM-size profile (most specific: RAM-backed buffers scale with available PSRAM) ---
83#if defined(PC_PSRAM_MB)
84#if PC_PSRAM_MB >= 32
85#include "esp/32mbpsram.h"
86#elif PC_PSRAM_MB >= 16
87#include "esp/16mbpsram.h"
88#elif PC_PSRAM_MB >= 8
89#include "esp/8mbpsram.h"
90#elif PC_PSRAM_MB >= 4
91#include "esp/4mbpsram.h"
92#elif PC_PSRAM_MB >= 2
93#include "esp/2mbpsram.h"
94#endif
95#endif
96
97// --- flash-size profile (flash-backed sizing scales with available flash) ---
98#if defined(PC_FLASH_MB)
99#if PC_FLASH_MB >= 32
100#include "esp/32mbflash.h"
101#elif PC_FLASH_MB >= 16
102#include "esp/16mbflash.h"
103#elif PC_FLASH_MB >= 8
104#include "esp/8mbflash.h"
105#elif PC_FLASH_MB >= 4
106#include "esp/4mbflash.h"
107#elif PC_FLASH_MB >= 2
108#include "esp/2mbflash.h"
109#endif
110#endif
111
112// --- chip profile (auto-selected from the SoC target macro; each pulls classic_defaults.h in
113// last as the universal sizing floor). Every macro name is uppercase with no hyphen/underscore
114// in the suffix (e.g. ...ESP32C61), verified against ESP-IDF's components/soc/<target>/.
115// S31/H4/H21 are preview targets (in ESP-IDF master, not a stable release yet). ---
116#if PC_VENDOR_ESP
117#if defined(CONFIG_IDF_TARGET_ESP32P4)
118#include "esp/p4_defaults.h"
119#elif defined(CONFIG_IDF_TARGET_ESP32S31)
120#include "esp/s31_defaults.h"
121#elif defined(CONFIG_IDF_TARGET_ESP32S3)
122#include "esp/s3_defaults.h"
123#elif defined(CONFIG_IDF_TARGET_ESP32S2)
124#include "esp/s2_defaults.h"
125#elif defined(CONFIG_IDF_TARGET_ESP32C2)
126#include "esp/c2_defaults.h"
127#elif defined(CONFIG_IDF_TARGET_ESP32C3)
128#include "esp/c3_defaults.h"
129#elif defined(CONFIG_IDF_TARGET_ESP32C5)
130#include "esp/c5_defaults.h"
131#elif defined(CONFIG_IDF_TARGET_ESP32C61)
132#include "esp/c61_defaults.h"
133#elif defined(CONFIG_IDF_TARGET_ESP32C6)
134#include "esp/c6_defaults.h"
135#elif defined(CONFIG_IDF_TARGET_ESP32H21)
136#include "esp/h21_defaults.h"
137#elif defined(CONFIG_IDF_TARGET_ESP32H2)
138#include "esp/h2_defaults.h"
139#elif defined(CONFIG_IDF_TARGET_ESP32H4)
140#include "esp/h4_defaults.h"
141#else
142// Classic ESP32 (no dedicated profile) lands on the universal floor.
143#include "classic_defaults.h"
144#endif
145#else
146// Non-ESP vendors (STM / RP / TI) and host/native builds: the universal sizing floor until per-vendor
147// profiles land (the multi-vendor portability track). Behavior-identical to the pre-selector path, which
148// fell through to classic_defaults.h whenever no CONFIG_IDF_TARGET_* macro was defined.
149#include "classic_defaults.h"
150#endif
151
152#endif // PROTOCORE_BOARD_PROFILE_H
16 MB flash profile - flash-backed default sizing.
16 MB PSRAM profile - larger RAM-backed pools than the 8 MB profile.
2 MB flash profile - the smallest flash step - flash-backed default sizing.
2 MB PSRAM profile - the smallest external-RAM step (e.g. classic WROVER, some C-series).
32 MB flash profile - flash-backed default sizing.
32 MB PSRAM profile - the largest RAM-backed pools.
4 MB flash profile - the common default density - flash-backed default sizing.
4 MB PSRAM profile - between the 2 MB and 8 MB steps.
8 MB flash profile - flash-backed default sizing.
8 MB PSRAM profile - scale the RAM-backed pools up past the chip's internal SRAM.
ESP32-C2 (ESP8684) die profile - single RISC-V, 272 KB SRAM, Wi-Fi 4 + BLE 5.0, no PSRAM.
ESP32-C3 die profile - single RISC-V, 400 KB SRAM, Wi-Fi 4 + BLE 5.0, no PSRAM.
ESP32-C5 die profile - single RISC-V (+LP), 384 KB SRAM, dual-band Wi-Fi 6, PSRAM.
ESP32-C61 die profile - single RISC-V, 320 KB SRAM, cost-optimized Wi-Fi 6 + BLE 5....
ESP32-C6 die profile - RISC-V HP + LP core, 512 KB SRAM, Wi-Fi 6 + BLE 5 + 802.15....
Classic ESP32 die profile + the universal conservative sizing floor.
ESP32-H21 die profile (PREVIEW) - single RISC-V, 320 KB SRAM, BLE 5 + 802.15.4, no Wi-Fi.
ESP32-H2 die profile - single RISC-V, 320 KB SRAM, BLE 5.0 + 802.15.4, NO Wi-Fi.
ESP32-H4 die profile (PREVIEW) - dual RISC-V, 384 KB SRAM, BLE 5.4 + 802.15.4, no Wi-Fi.
ESP32-P4 die profile - dual RISC-V + FPU up to 400 MHz, 768 KB L2MEM, no radio.
The one vendor/die selector for the whole library.
ESP32-S2 die profile - single Xtensa LX7, 320 KB SRAM, Wi-Fi 4 only (no Bluetooth).
ESP32-S31 die profile (PREVIEW) - dual RISC-V up to 320 MHz, 512 KB SRAM, multiprotocol.
ESP32-S3 die profile - dual Xtensa LX7, 512 KB SRAM, Wi-Fi 4 + BLE 5.0, Octal PSRAM.