ProtoCore v0.0.1
Deterministic, zero-heap network stack for embedded targets
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8mbpsram.h
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1// Copyright (C) 2026 Douglas Quigg (dstroy0) <dquigg123@gmail.com>
2// SPDX-License-Identifier: AGPL-3.0-or-later
3
4/**
5 * @file 8mbpsram.h
6 * @brief 8 MB PSRAM profile - scale the RAM-backed pools up past the chip's internal SRAM.
7 *
8 * Included before the chip profile, so these win for the memory-bound sizes. Note: growing
9 * the L1 slot count only pays off once the cache actually lives in PSRAM; until an edge-cache
10 * PSRAM-resident placement lands, the internal DRAM budget still bounds these, so the bumps
11 * here stay conservative. `#ifndef`-guarded, so your -D overrides still win.
12 */
13
14#ifndef PROTOCORE_8MBPSRAM_H
15#define PROTOCORE_8MBPSRAM_H
16
17// PSRAM fitted: move the big TLS/HTTP-2/zlib pools off internal DRAM and raise concurrency.
18#ifndef PC_TLS_ARENA_IN_PSRAM
19#define PC_TLS_ARENA_IN_PSRAM 1
20#endif
21#ifndef PC_H2_POOL_IN_PSRAM
22#define PC_H2_POOL_IN_PSRAM 1
23#endif
24#ifndef PC_SSH_ZLIB_IN_PSRAM
25#define PC_SSH_ZLIB_IN_PSRAM 1
26#endif
27#ifndef MAX_TLS_CONNS
28#define MAX_TLS_CONNS 6
29#endif
30#ifndef PC_H2_MAX_STREAMS
31#define PC_H2_MAX_STREAMS 16
32#endif
33#ifndef PC_H3_MAX_STREAMS
34#define PC_H3_MAX_STREAMS 16
35#endif
36#ifndef PC_EDGE_CACHE_SLOTS
37#define PC_EDGE_CACHE_SLOTS 16
38#endif
39#ifndef PC_EDGE_BODY_MAX
40#define PC_EDGE_BODY_MAX 8192
41#endif
42
43#endif // PROTOCORE_8MBPSRAM_H