praet_platform_detection.h File Reference

Which architecture this is being built for, and what that architecture gives a clock. More...

#include "mmgr.h"

Go to the source code of this file.

Macros
#define	PRAET_PLATFORM_ARM
	Set where this is an ARM build, in either execution state.
#define	PRAET_PLATFORM_RISCV
	Set where this is a RISC-V build, at any register width.
#define	PRAET_PLATFORM_XTENSA
	Set where this is an Xtensa build.
#define	PRAET_PLATFORM_HOST
	Set where this is none of the three, which is a host build.
#define	PRAET_PLATFORM_NAME
	What to call this architecture in a diagnostic.
#define	PRAET_PLATFORM_HAS_CYCLE_COUNTER
	Set where the architecture defines a counter the port can read without the caller running one.
#define	PRAET_PLATFORM_XLEN
	Bits in this architecture's general purpose register.
#define	PRAET_PLATFORM_UNALIGNED_LOADS
	Set where the architecture loads and stores at an address that is not aligned to the size.
#define	PRAET_PLATFORM_CLOCK_CORE
	The core a platform default pins a timer to.

Detailed Description

Which architecture this is being built for, and what that architecture gives a clock.

Author

dstroy0 (Douglas Quigg) dquig.nosp@m.g123.nosp@m.@gmai.nosp@m.l.co.nosp@m.m

Date

2026-09-01

Note

Nothing below names a part, a vendor or a board, and nothing should. A list of parts covers the ones somebody thought of on the day they wrote it and silently misses every part released afterwards. What is tested here is the architecture level, which every member of a family defines - an ATSAMD21 answers the ARMv6-M question the same way every other Cortex-M0+ does, and a part nobody here has heard of answers it too.

The three families are the ones this library targets: ARM, RISC-V and Xtensa, all through GCC or clang. A build that is none of them is a host build, which is where the suites run.

The architecture tests below exist for the clock. embedded_types answers the compiler and width questions, and does not say whether a cycle counter exists.

Sources for the macros used below: Arm C Language Extensions https://arm-software.github.io/acle/main/acle.html RISC-V C API specification https://github.com/riscv-non-isa/riscv-c-api-doc GCC gcc/config/xtensa/xtensa.h TARGET_CPU_CPP_BUILTINS

Definition in file praet_platform_detection.h.

Macro Definition Documentation

PRAET_PLATFORM_ARM

#define PRAET_PLATFORM_ARM

Set where this is an ARM build, in either execution state.

Note

arm covers every 32-bit ARM back to ARMv4, and aarch64 covers the 64-bit state. ACLE leaves both in place, and so testing the pair catches every ARM subfamily without naming one.

Definition at line 42 of file praet_platform_detection.h.

PRAET_PLATFORM_RISCV

#define PRAET_PLATFORM_RISCV

Set where this is a RISC-V build, at any register width.

Note

The RISC-V C API defines __riscv as 1 on every RISC-V target. There is no second name and no per-vendor variant of it.

Definition at line 54 of file praet_platform_detection.h.

PRAET_PLATFORM_XTENSA

#define PRAET_PLATFORM_XTENSA

Set where this is an Xtensa build.

Note

GCC predefines both names unconditionally for Xtensa. Both are tested because a clang build for Xtensa is a separate front end and there is no reason to depend on it agreeing about which one to emit.

Definition at line 67 of file praet_platform_detection.h.

PRAET_PLATFORM_HOST

#define PRAET_PLATFORM_HOST

Set where this is none of the three, which is a host build.

Definition at line 74 of file praet_platform_detection.h.

PRAET_PLATFORM_NAME

#define PRAET_PLATFORM_NAME

What to call this architecture in a diagnostic.

Note

A host build. The suites run here, and a host has a clock the caller reaches through the standard library. This library has nothing to pin there.

Definition at line 283 of file praet_platform_detection.h.

PRAET_PLATFORM_HAS_CYCLE_COUNTER

#define PRAET_PLATFORM_HAS_CYCLE_COUNTER

Set where the architecture defines a counter the port can read without the caller running one.

Note

Zero, and not because a host has no counter. A host build has no core to pin a timer to and no architectural register to read, and so the clock is the caller's - and that leaves a host build take the same arm a Cortex-M0 does, for the same reason.

Definition at line 293 of file praet_platform_detection.h.

PRAET_PLATFORM_XLEN

#define PRAET_PLATFORM_XLEN

Bits in this architecture's general purpose register.

Note

Off the pointer's width, read from UINTPTR_MAX, which <stdint.h> gives every C11 compiler as a constant the preprocessor compares. A host is whatever the machine running the suites is, and so there is nothing else to read it from.

Definition at line 307 of file praet_platform_detection.h.

PRAET_PLATFORM_UNALIGNED_LOADS

#define PRAET_PLATFORM_UNALIGNED_LOADS

Set where the architecture loads and stores at an address that is not aligned to the size.

Definition at line 313 of file praet_platform_detection.h.

PRAET_PLATFORM_CLOCK_CORE

#define PRAET_PLATFORM_CLOCK_CORE

The core a platform default pins a timer to.

Note

Core zero, on every family. A part with one core has it and a part with several starts at it, and so it is the number that exists everywhere. It is the right one on no part in particular. Which core is right is the caller's to say, and PRAET_CLOCK_CORE is where they say it.

Definition at line 330 of file praet_platform_detection.h.