DeterministicESPAsyncWebServer v6.28.0
Zero-allocation, bounded-execution async HTTP server for ESP32
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edge_cache_sd.h File Reference

CDN edge-cache tier - L2 SD persistence (DETWS_ENABLE_EDGE_CACHE && DETWS_ENABLE_DBM). More...

#include "ServerConfig.h"

Go to the source code of this file.

Detailed Description

CDN edge-cache tier - L2 SD persistence (DETWS_ENABLE_EDGE_CACHE && DETWS_ENABLE_DBM).

The persistent second tier behind the bounded L1 RAM store (edge_cache): an evicted L1 entry is written back to a dbm key-value store on the WAL (services/dbm, SD-card backed on device, a RAM WalDev for host tests), and an L1 miss is served by promoting the entry back from L2. Because the store is log-structured on the WAL, the cached set survives a reboot (dbm rebuilds its index by replaying the log on open).

The L2 key is the entry's 32-byte SHA-256 digest (== DETWS_DBM_KEY_MAX), so no key is re-derived. The value is a compact, versioned, little-endian serialization of the entry's response metadata + body.

These are pure functions over a caller-owned dbm handle and a caller-owned scratch buffer (no file-scope state); the proxy glue (edge_cache_proxy) owns the dbm and the buffer and installs the write-back / promote wiring.

Reboot note: the monotonic insert time is meaningless across a reboot (no wall clock), so a promoted entry is always treated as stale by the caller and revalidated - which is why only entries carrying a validator (ETag / Last-Modified) are spilled: they are exactly the ones a cheap 304 can refresh.

Author
Douglas Quigg (dstroy0)
Date
2026

Definition in file edge_cache_sd.h.