ProtoCore
v0.0.1
Deterministic, zero-heap network stack for embedded targets
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s3_defaults.h
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// Copyright (C) 2026 Douglas Quigg (dstroy0) <dquigg123@gmail.com>
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// SPDX-License-Identifier: AGPL-3.0-or-later
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/**
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* @file s3_defaults.h
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* @brief ESP32-S3 die profile - dual Xtensa LX7, 512 KB SRAM, Wi-Fi 4 + BLE 5.0, Octal PSRAM.
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*
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* Roomier usable DRAM than the classic ESP32 plus AI/vector DSP instructions, so the RAM-backed
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* pools get a modest bump even with no PSRAM fitted (a PSRAM profile, included first, scales them
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* further). Crypto HW: AES, SHA, RSA/MPI, HMAC, DS (no ECC/ECDSA). classic_defaults.h is pulled
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* in last as the sizing floor; every macro is `#ifndef`-guarded so a -D override wins.
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*/
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#ifndef PROTOCORE_S3_DEFAULTS_H
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#define PROTOCORE_S3_DEFAULTS_H
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// --- HW crypto accelerators ---
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#ifndef PC_HW_AES
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#define PC_HW_AES 1
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#endif
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#ifndef PC_HW_SHA
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#define PC_HW_SHA 1
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#endif
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#ifndef PC_HW_RSA
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#define PC_HW_RSA 1
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#endif
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#ifndef PC_HW_ECC
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#define PC_HW_ECC 0
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#endif
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#ifndef PC_HW_ECDSA
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#define PC_HW_ECDSA 0
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#endif
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#ifndef PC_HW_HMAC
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#define PC_HW_HMAC 1
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#endif
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#ifndef PC_HW_DS
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#define PC_HW_DS 1
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#endif
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// --- Sizing (bumped over the classic floor to use the S3's ~400 KB usable DRAM) ---
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// These are internal-SRAM-budget values (no PSRAM assumed); a PSRAM-size profile, included first,
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// scales the RAM-backed buffers further and moves the big TLS / HTTP-2 pools off-chip.
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// Connection pools + per-connection buffers.
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#ifndef MAX_CONNS
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#define MAX_CONNS 12
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#endif
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#ifndef RX_BUF_SIZE
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#define RX_BUF_SIZE 2048
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#endif
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#ifndef PC_SCRATCH_ARENA_SIZE
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#define PC_SCRATCH_ARENA_SIZE 12288
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#endif
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#ifndef PC_CLIENT_RX_BUF
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#define PC_CLIENT_RX_BUF 8192
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#endif
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// HTTP surface (roomier route/header/body budgets).
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#ifndef MAX_ROUTES
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#define MAX_ROUTES 32
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#endif
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#ifndef MAX_HEADERS
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#define MAX_HEADERS 16
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#endif
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#ifndef BODY_BUF_SIZE
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#define BODY_BUF_SIZE 1024
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#endif
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// WebSocket / SSE fan-out.
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#ifndef MAX_WS_CONNS
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#define MAX_WS_CONNS 4
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#endif
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#ifndef MAX_SSE_CONNS
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#define MAX_SSE_CONNS 4
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#endif
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// TLS: one handshake on the internal-DRAM arena (the ~48 KB arena + ~32 KB/extra conn would overflow
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// internal DRAM); a PSRAM profile raises this with the arena moved off-chip and auto-sized.
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#ifndef MAX_TLS_CONNS
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#define MAX_TLS_CONNS 1
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#endif
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// SSH server + reverse-SSH client.
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#ifndef MAX_SSH_CONNS
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#define MAX_SSH_CONNS 2
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#endif
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#ifndef PC_SSH_MAX_CHANNELS
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#define PC_SSH_MAX_CHANNELS 4
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#endif
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#ifndef PC_SSH_CLIENT_MAX_CHANNELS
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#define PC_SSH_CLIENT_MAX_CHANNELS 6
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#endif
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// Edge cache + mesh (RAM-backed L1).
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#ifndef PC_EDGE_CACHE_SLOTS
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#define PC_EDGE_CACHE_SLOTS 8
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#endif
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#ifndef PC_EDGE_BODY_MAX
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#define PC_EDGE_BODY_MAX 4096
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#endif
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#ifndef PC_EDGE_FETCH_SLOTS
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#define PC_EDGE_FETCH_SLOTS 3
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#endif
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#ifndef PC_MESH_MAX_PEERS
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#define PC_MESH_MAX_PEERS 6
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#endif
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#ifndef PC_MESH_MAX_CONNS
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#define PC_MESH_MAX_CONNS 2
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#endif
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#include "../classic_defaults.h"
// sizing floor for anything not set above
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#endif
// PROTOCORE_S3_DEFAULTS_H
src
board_drivers
board_profiles
esp
s3_defaults.h
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