ProtoCore v0.0.1
Deterministic, zero-heap network stack for embedded targets
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p4_defaults.h
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1// Copyright (C) 2026 Douglas Quigg (dstroy0) <dquigg123@gmail.com>
2// SPDX-License-Identifier: AGPL-3.0-or-later
3
4/**
5 * @file p4_defaults.h
6 * @brief ESP32-P4 die profile - dual RISC-V + FPU up to 400 MHz, 768 KB L2MEM, no radio.
7 *
8 * The high-performance host MCU: dual RISC-V with FPU/AI, MIPI-CSI/DSI, USB-HS, and the largest
9 * internal SRAM (768 KB L2MEM). It has NO built-in radio (pairs with a companion Wi-Fi/BT chip),
10 * and is commonly fitted with high-bandwidth PSRAM up to 32 MB (a PSRAM profile, included first,
11 * scales further). Full crypto HW: AES, SHA, RSA/MPI (4096-bit), ECC, ECDSA, HMAC, DS.
12 * classic_defaults.h is the sizing floor; every macro is `#ifndef`-guarded.
13 */
14
15#ifndef PROTOCORE_P4_DEFAULTS_H
16#define PROTOCORE_P4_DEFAULTS_H
17
18// --- HW crypto accelerators (full suite, RSA up to 4096-bit) ---
19#ifndef PC_HW_AES
20#define PC_HW_AES 1
21#endif
22#ifndef PC_HW_SHA
23#define PC_HW_SHA 1
24#endif
25#ifndef PC_HW_RSA
26#define PC_HW_RSA 1
27#endif
28#ifndef PC_HW_ECC
29#define PC_HW_ECC 1
30#endif
31#ifndef PC_HW_ECDSA
32#define PC_HW_ECDSA 1
33#endif
34#ifndef PC_HW_HMAC
35#define PC_HW_HMAC 1
36#endif
37#ifndef PC_HW_DS
38#define PC_HW_DS 1
39#endif
40
41// --- Sizing (largest no-PSRAM bump: 768 KB L2MEM + fast dual core) ---
42// Internal-SRAM-budget values; a PSRAM-size profile (included first) scales the RAM-backed buffers
43// further and moves the big TLS / HTTP-2 pools to the (up to 32 MB) high-bandwidth PSRAM.
44
45// Connection pools + per-connection buffers.
46#ifndef MAX_CONNS
47#define MAX_CONNS 16
48#endif
49#ifndef RX_BUF_SIZE
50#define RX_BUF_SIZE 2048
51#endif
52#ifndef PC_SCRATCH_ARENA_SIZE
53#define PC_SCRATCH_ARENA_SIZE 16384
54#endif
55#ifndef PC_CLIENT_RX_BUF
56#define PC_CLIENT_RX_BUF 8192
57#endif
58
59// HTTP surface.
60#ifndef MAX_ROUTES
61#define MAX_ROUTES 48
62#endif
63#ifndef MAX_HEADERS
64#define MAX_HEADERS 24
65#endif
66#ifndef BODY_BUF_SIZE
67#define BODY_BUF_SIZE 2048
68#endif
69
70// WebSocket / SSE fan-out.
71#ifndef MAX_WS_CONNS
72#define MAX_WS_CONNS 8
73#endif
74#ifndef MAX_SSE_CONNS
75#define MAX_SSE_CONNS 8
76#endif
77
78// TLS: one handshake on the internal-DRAM arena; a PSRAM profile raises this with the arena in PSRAM.
79#ifndef MAX_TLS_CONNS
80#define MAX_TLS_CONNS 1
81#endif
82
83// SSH server + reverse-SSH client.
84#ifndef MAX_SSH_CONNS
85#define MAX_SSH_CONNS 3
86#endif
87#ifndef PC_SSH_MAX_CHANNELS
88#define PC_SSH_MAX_CHANNELS 6
89#endif
90#ifndef PC_SSH_CLIENT_MAX_CHANNELS
91#define PC_SSH_CLIENT_MAX_CHANNELS 8
92#endif
93
94// Edge cache + mesh (RAM-backed L1).
95#ifndef PC_EDGE_CACHE_SLOTS
96#define PC_EDGE_CACHE_SLOTS 12
97#endif
98#ifndef PC_EDGE_BODY_MAX
99#define PC_EDGE_BODY_MAX 8192
100#endif
101#ifndef PC_EDGE_FETCH_SLOTS
102#define PC_EDGE_FETCH_SLOTS 4
103#endif
104#ifndef PC_MESH_MAX_PEERS
105#define PC_MESH_MAX_PEERS 8
106#endif
107#ifndef PC_MESH_MAX_CONNS
108#define PC_MESH_MAX_CONNS 2
109#endif
110
111#include "../classic_defaults.h"
112#endif // PROTOCORE_P4_DEFAULTS_H