ProtoCore v0.0.2
Deterministic, zero-heap network stack for embedded targets
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h2_defaults.h
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1// Copyright (C) 2026 Douglas Quigg (dstroy0) <dquigg123@gmail.com>
2// SPDX-License-Identifier: AGPL-3.0-or-later
3
4/**
5 * @file h2_defaults.h
6 * @brief ESP32-H2 die profile - single RISC-V, 320 KB SRAM, BLE 5.0 + 802.15.4, NO Wi-Fi.
7 *
8 * A Thread/Zigbee/Matter radio part: 802.15.4 + BLE 5.0, no Wi-Fi. 320 KB SRAM, single core, so it
9 * stays at the conservative floor. Full crypto HW: AES, SHA, RSA/MPI, ECC, ECDSA, HMAC, DS. No
10 * PSRAM. classic_defaults.h is the sizing floor; every macro is `#ifndef`-guarded.
11 */
12
13#ifndef PROTOCORE_H2_DEFAULTS_H
14#define PROTOCORE_H2_DEFAULTS_H
15
16// --- HW crypto accelerators (full suite) ---
17#ifndef PC_HW_AES
18#define PC_HW_AES 1
19#endif
20#ifndef PC_HW_SHA
21#define PC_HW_SHA 1
22#endif
23#ifndef PC_HW_RSA
24#define PC_HW_RSA 1
25#endif
26#ifndef PC_HW_ECC
27#define PC_HW_ECC 1
28#endif
29#ifndef PC_HW_ECDSA
30#define PC_HW_ECDSA 1
31#endif
32#ifndef PC_HW_HMAC
33#define PC_HW_HMAC 1
34#endif
35#ifndef PC_HW_DS
36#define PC_HW_DS 1
37#endif
38
39// --- Sizing (conservative: single core, 320 KB SRAM, no Wi-Fi) ---
40// Internal-SRAM-budget values (no PSRAM assumed); a PSRAM-size profile, included first, scales the
41// RAM-backed buffers further and moves the big TLS / HTTP-2 pools off-chip.
42
43// Connection pools + per-connection buffers.
44#ifndef MAX_CONNS
45#define MAX_CONNS 8
46#endif
47#ifndef RX_BUF_SIZE
48#define RX_BUF_SIZE 1024
49#endif
50#ifndef PC_SCRATCH_ARENA_SIZE
51#define PC_SCRATCH_ARENA_SIZE 8192
52#endif
53#ifndef PC_CLIENT_RX_BUF
54#define PC_CLIENT_RX_BUF 4096
55#endif
56
57// HTTP surface.
58#ifndef MAX_ROUTES
59#define MAX_ROUTES 16
60#endif
61#ifndef MAX_HEADERS
62#define MAX_HEADERS 8
63#endif
64#ifndef BODY_BUF_SIZE
65#define BODY_BUF_SIZE 256
66#endif
67
68// WebSocket / SSE fan-out.
69#ifndef MAX_WS_CONNS
70#define MAX_WS_CONNS 2
71#endif
72#ifndef MAX_SSE_CONNS
73#define MAX_SSE_CONNS 2
74#endif
75
76// TLS: a single handshake fits the tight internal SRAM; a PSRAM profile raises this and moves the arena.
77#ifndef MAX_TLS_CONNS
78#define MAX_TLS_CONNS 1
79#endif
80
81// SSH server + reverse-SSH client.
82#ifndef MAX_SSH_CONNS
83#define MAX_SSH_CONNS 1
84#endif
85#ifndef PC_SSH_MAX_CHANNELS
86#define PC_SSH_MAX_CHANNELS 2
87#endif
88#ifndef PC_SSH_CLIENT_MAX_CHANNELS
89#define PC_SSH_CLIENT_MAX_CHANNELS 2
90#endif
91
92// Edge cache + mesh (RAM-backed L1).
93#ifndef PC_EDGE_CACHE_SLOTS
94#define PC_EDGE_CACHE_SLOTS 4
95#endif
96#ifndef PC_EDGE_BODY_MAX
97#define PC_EDGE_BODY_MAX 2048
98#endif
99#ifndef PC_EDGE_FETCH_SLOTS
100#define PC_EDGE_FETCH_SLOTS 2
101#endif
102#ifndef PC_MESH_MAX_PEERS
103#define PC_MESH_MAX_PEERS 4
104#endif
105#ifndef PC_MESH_MAX_CONNS
106#define PC_MESH_MAX_CONNS 1
107#endif
108
109#include "../classic_defaults.h"
110#endif // PROTOCORE_H2_DEFAULTS_H