ProtoCore v0.0.1
Deterministic, zero-heap network stack for embedded targets
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classic_defaults.h
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1// Copyright (C) 2026 Douglas Quigg (dstroy0) <dquigg123@gmail.com>
2// SPDX-License-Identifier: AGPL-3.0-or-later
3
4/**
5 * @file classic_defaults.h
6 * @brief Classic ESP32 die profile + the universal conservative sizing floor.
7 *
8 * Dual Xtensa LX6, 520 KB internal SRAM (~122 KB usable `dram0_0_seg` after IRAM/reserved),
9 * no PSRAM by default. This is the smallest usable-DRAM budget of the supported targets, so its
10 * sizing doubles as the floor every other chip profile includes last (they override upward).
11 * Sizing values match the library's historical flat defaults, so classic-ESP32 and host builds
12 * are unchanged.
13 *
14 * The crypto-HW flags below are the classic ESP32's accelerator set (AES, SHA, RSA/MPI - no
15 * ECC/ECDSA/HMAC/DS). Every chip profile that includes this file as the floor first defines its
16 * OWN `PC_HW_*` flags, so these apply only to the classic-ESP32 (and, harmlessly, host) path.
17 * All macros are `#ifndef`-guarded, so a -D override or a richer variant profile always wins.
18 */
19
20#ifndef PROTOCORE_CLASSIC_DEFAULTS_H
21#define PROTOCORE_CLASSIC_DEFAULTS_H
22
23// --- HW crypto accelerators (classic ESP32: AES + SHA + RSA/MPI only) ---
24#ifndef PC_HW_AES
25#define PC_HW_AES 1
26#endif
27#ifndef PC_HW_SHA
28#define PC_HW_SHA 1
29#endif
30#ifndef PC_HW_RSA
31#define PC_HW_RSA 1 // the MPI/bignum accelerator
32#endif
33#ifndef PC_HW_ECC
34#define PC_HW_ECC 0
35#endif
36#ifndef PC_HW_ECDSA
37#define PC_HW_ECDSA 0
38#endif
39#ifndef PC_HW_HMAC
40#define PC_HW_HMAC 0
41#endif
42#ifndef PC_HW_DS
43#define PC_HW_DS 0 // Digital Signature peripheral
44#endif
45
46// --- Edge cache (RAM-backed L1: each slot holds one cached object, ~2.6 KB) ---
47#ifndef PC_EDGE_CACHE_SLOTS
48#define PC_EDGE_CACHE_SLOTS 4 // L1 RAM entries
49#endif
50#ifndef PC_EDGE_BODY_MAX
51#define PC_EDGE_BODY_MAX 2048 // largest cacheable body in bytes (per L1 entry)
52#endif
53#ifndef PC_EDGE_FETCH_SLOTS
54#define PC_EDGE_FETCH_SLOTS 2 // concurrent in-flight origin fetches (<= PC_CLIENT_CONNS)
55#endif
56
57// --- Edge mesh (sibling-cache distribution) ---
58#ifndef PC_MESH_MAX_PEERS
59#define PC_MESH_MAX_PEERS 4 // sibling peers queried on a local miss (in series, first hit wins)
60#endif
61#ifndef PC_MESH_MAX_CONNS
62#define PC_MESH_MAX_CONNS 1 // concurrent inbound peer-serve connections
63#endif
64
65#endif // PROTOCORE_CLASSIC_DEFAULTS_H