ProtoCore v0.0.2
Deterministic, zero-heap network stack for embedded targets
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c5_defaults.h
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1// Copyright (C) 2026 Douglas Quigg (dstroy0) <dquigg123@gmail.com>
2// SPDX-License-Identifier: AGPL-3.0-or-later
3
4/**
5 * @file c5_defaults.h
6 * @brief ESP32-C5 die profile - single RISC-V (+LP), 384 KB SRAM, dual-band Wi-Fi 6, PSRAM.
7 *
8 * First RISC-V part with 2.4 + 5 GHz dual-band Wi-Fi 6 (plus BLE 5.0 and 802.15.4). 384 KB HP SRAM
9 * with a roomy usable-DRAM map, so a small bump over the floor. Full crypto HW: AES, SHA, RSA/MPI,
10 * ECC, ECDSA, HMAC, DS. Supports external PSRAM. classic_defaults.h is the sizing floor; every
11 * macro is `#ifndef`-guarded.
12 */
13
14#ifndef PROTOCORE_C5_DEFAULTS_H
15#define PROTOCORE_C5_DEFAULTS_H
16
17// --- HW crypto accelerators (full suite) ---
18#ifndef PC_HW_AES
19#define PC_HW_AES 1
20#endif
21#ifndef PC_HW_SHA
22#define PC_HW_SHA 1
23#endif
24#ifndef PC_HW_RSA
25#define PC_HW_RSA 1
26#endif
27#ifndef PC_HW_ECC
28#define PC_HW_ECC 1
29#endif
30#ifndef PC_HW_ECDSA
31#define PC_HW_ECDSA 1
32#endif
33#ifndef PC_HW_HMAC
34#define PC_HW_HMAC 1
35#endif
36#ifndef PC_HW_DS
37#define PC_HW_DS 1
38#endif
39
40// --- Sizing (bump over the floor; single core +LP, 384 KB SRAM) ---
41// Internal-SRAM-budget values (no PSRAM assumed); a PSRAM-size profile, included first, scales the
42// RAM-backed buffers further and moves the big TLS / HTTP-2 pools off-chip.
43
44// Connection pools + per-connection buffers.
45#ifndef MAX_CONNS
46#define MAX_CONNS 12
47#endif
48#ifndef RX_BUF_SIZE
49#define RX_BUF_SIZE 1536
50#endif
51#ifndef PC_SCRATCH_ARENA_SIZE
52#define PC_SCRATCH_ARENA_SIZE 10240
53#endif
54#ifndef PC_CLIENT_RX_BUF
55#define PC_CLIENT_RX_BUF 8192
56#endif
57
58// HTTP surface.
59#ifndef MAX_ROUTES
60#define MAX_ROUTES 24
61#endif
62#ifndef MAX_HEADERS
63#define MAX_HEADERS 12
64#endif
65#ifndef BODY_BUF_SIZE
66#define BODY_BUF_SIZE 512
67#endif
68
69// WebSocket / SSE fan-out.
70#ifndef MAX_WS_CONNS
71#define MAX_WS_CONNS 4
72#endif
73#ifndef MAX_SSE_CONNS
74#define MAX_SSE_CONNS 4
75#endif
76
77// TLS: one handshake on the internal-DRAM arena; a PSRAM profile raises this with the arena in PSRAM.
78#ifndef MAX_TLS_CONNS
79#define MAX_TLS_CONNS 1
80#endif
81
82// SSH server + reverse-SSH client.
83#ifndef MAX_SSH_CONNS
84#define MAX_SSH_CONNS 2
85#endif
86#ifndef PC_SSH_MAX_CHANNELS
87#define PC_SSH_MAX_CHANNELS 4
88#endif
89#ifndef PC_SSH_CLIENT_MAX_CHANNELS
90#define PC_SSH_CLIENT_MAX_CHANNELS 4
91#endif
92
93// Edge cache + mesh (RAM-backed L1).
94#ifndef PC_EDGE_CACHE_SLOTS
95#define PC_EDGE_CACHE_SLOTS 6
96#endif
97#ifndef PC_EDGE_BODY_MAX
98#define PC_EDGE_BODY_MAX 4096
99#endif
100#ifndef PC_EDGE_FETCH_SLOTS
101#define PC_EDGE_FETCH_SLOTS 3
102#endif
103#ifndef PC_MESH_MAX_PEERS
104#define PC_MESH_MAX_PEERS 6
105#endif
106#ifndef PC_MESH_MAX_CONNS
107#define PC_MESH_MAX_CONNS 1
108#endif
109
110#include "../classic_defaults.h"
111#endif // PROTOCORE_C5_DEFAULTS_H