ProtoCore v0.0.1
Deterministic, zero-heap network stack for embedded targets
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c2_defaults.h
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1// Copyright (C) 2026 Douglas Quigg (dstroy0) <dquigg123@gmail.com>
2// SPDX-License-Identifier: AGPL-3.0-or-later
3
4/**
5 * @file c2_defaults.h
6 * @brief ESP32-C2 (ESP8684) die profile - single RISC-V, 272 KB SRAM, Wi-Fi 4 + BLE 5.0, no PSRAM.
7 *
8 * The cheapest/smallest die: 272 KB SRAM is tighter than the classic ESP32's usable DRAM, so it
9 * stays at the conservative floor (no sizing bump). Reduced crypto: SHA + ECC only - there is NO
10 * general-purpose AES peripheral (AES exists only as the XTS flash-encryption engine) and NO
11 * RSA/MPI, HMAC or DS, so secure boot is ECC-based. Do not assume "any ESP32 has AES/RSA". No PSRAM.
12 * classic_defaults.h is pulled in last as the sizing floor; every macro is `#ifndef`-guarded.
13 */
14
15#ifndef PROTOCORE_C2_DEFAULTS_H
16#define PROTOCORE_C2_DEFAULTS_H
17
18// --- HW crypto accelerators (reduced: SHA + ECC only; no general AES, no RSA/HMAC/DS) ---
19#ifndef PC_HW_AES
20#define PC_HW_AES 0
21#endif
22#ifndef PC_HW_SHA
23#define PC_HW_SHA 1
24#endif
25#ifndef PC_HW_RSA
26#define PC_HW_RSA 0
27#endif
28#ifndef PC_HW_ECC
29#define PC_HW_ECC 1
30#endif
31#ifndef PC_HW_ECDSA
32#define PC_HW_ECDSA 0
33#endif
34#ifndef PC_HW_HMAC
35#define PC_HW_HMAC 0
36#endif
37#ifndef PC_HW_DS
38#define PC_HW_DS 0
39#endif
40
41// --- Sizing (conservative: single core, 272 KB SRAM - the tightest die) ---
42// Internal-SRAM-budget values (no PSRAM assumed); a PSRAM-size profile, included first, scales the
43// RAM-backed buffers further and moves the big TLS / HTTP-2 pools off-chip.
44
45// Connection pools + per-connection buffers.
46#ifndef MAX_CONNS
47#define MAX_CONNS 8
48#endif
49#ifndef RX_BUF_SIZE
50#define RX_BUF_SIZE 1024
51#endif
52#ifndef PC_SCRATCH_ARENA_SIZE
53#define PC_SCRATCH_ARENA_SIZE 8192
54#endif
55#ifndef PC_CLIENT_RX_BUF
56#define PC_CLIENT_RX_BUF 4096
57#endif
58
59// HTTP surface.
60#ifndef MAX_ROUTES
61#define MAX_ROUTES 16
62#endif
63#ifndef MAX_HEADERS
64#define MAX_HEADERS 8
65#endif
66#ifndef BODY_BUF_SIZE
67#define BODY_BUF_SIZE 256
68#endif
69
70// WebSocket / SSE fan-out.
71#ifndef MAX_WS_CONNS
72#define MAX_WS_CONNS 2
73#endif
74#ifndef MAX_SSE_CONNS
75#define MAX_SSE_CONNS 2
76#endif
77
78// TLS: a single handshake fits the tight internal SRAM; a PSRAM profile raises this and moves the arena.
79#ifndef MAX_TLS_CONNS
80#define MAX_TLS_CONNS 1
81#endif
82
83// SSH server + reverse-SSH client.
84#ifndef MAX_SSH_CONNS
85#define MAX_SSH_CONNS 1
86#endif
87#ifndef PC_SSH_MAX_CHANNELS
88#define PC_SSH_MAX_CHANNELS 2
89#endif
90#ifndef PC_SSH_CLIENT_MAX_CHANNELS
91#define PC_SSH_CLIENT_MAX_CHANNELS 2
92#endif
93
94// Edge cache + mesh (RAM-backed L1).
95#ifndef PC_EDGE_CACHE_SLOTS
96#define PC_EDGE_CACHE_SLOTS 4
97#endif
98#ifndef PC_EDGE_BODY_MAX
99#define PC_EDGE_BODY_MAX 2048
100#endif
101#ifndef PC_EDGE_FETCH_SLOTS
102#define PC_EDGE_FETCH_SLOTS 2
103#endif
104#ifndef PC_MESH_MAX_PEERS
105#define PC_MESH_MAX_PEERS 4
106#endif
107#ifndef PC_MESH_MAX_CONNS
108#define PC_MESH_MAX_CONNS 1
109#endif
110
111#include "../classic_defaults.h"
112#endif // PROTOCORE_C2_DEFAULTS_H