22#ifndef DETERMINISTICESPASYNCWEBSERVER_FDC2214_H
23#define DETERMINISTICESPASYNCWEBSERVER_FDC2214_H
29#define FDC2214_REG_DATA_CH0_MSB 0x00
30#define FDC2214_REG_DATA_CH0_LSB 0x01
31#define FDC2214_REG_RCOUNT_CH0 0x08
32#define FDC2214_REG_SETTLECOUNT_CH0 0x10
33#define FDC2214_REG_CLOCK_DIVIDERS_CH0 0x14
34#define FDC2214_REG_STATUS 0x18
35#define FDC2214_REG_ERROR_CONFIG 0x19
36#define FDC2214_REG_CONFIG 0x1A
37#define FDC2214_REG_MUX_CONFIG 0x1B
38#define FDC2214_REG_DRIVE_CURRENT_CH0 0x1E
39#define FDC2214_REG_MANUFACTURER_ID 0x7E
40#define FDC2214_REG_DEVICE_ID 0x7F
42#define FDC2214_MANUFACTURER_ID 0x5449
43#define FDC2214_DEVICE_ID 0x3055
46#define FDC2214_CONFIG_MAX 21
uint32_t fdc2214_data(uint16_t msb_reg, uint16_t lsb_reg)
Combine a DATA MSB register (low 12 bits) and DATA LSB register into the 28-bit result.
uint8_t fdc2214_error(uint16_t msb_reg)
The 4 error flags from the top of a DATA MSB register (bits 15:12).
bool fdc2214_read_ch0(uint32_t *out)
Read channel 0's 28-bit conversion result into out.
bool fdc2214_begin(uint8_t addr, uint16_t rcount, uint16_t settlecount)
Verify the device id and apply the CH0 config at addr.
size_t fdc2214_build_config(uint8_t *buf, size_t cap, uint16_t rcount, uint16_t settlecount)
Emit a single-channel (CH0) continuous-conversion bring-up as (reg, val_msb, val_lsb) triples.
uint64_t fdc2214_sensor_freq_hz(uint32_t data28, uint32_t fref_hz)
Sensor frequency in Hz for a 28-bit result against a reference clock: data / 2^28 * fref.